The present invention relates to the generation of clocking signals. More particularly, the present invention pertains to transitioning from one clock domain to another using a multiplexer.
In digital circuits, a clocking signal is a signal that fluctuates between a high signal value (i.e., a binary xe2x80x9c1xe2x80x9d) and a low signal value (i.e., a binary xe2x80x9c0xe2x80x9d) with a given frequency. The xe2x80x9cdutyxe2x80x9d cycle of the signal reflect how long a signal remains at a logic xe2x80x9c1xe2x80x9d versus how long a signal remains at a logic xe2x80x9c0xe2x80x9d during one period. In many systems, the clocking signal has a 50% duty cycle (i.e., the clocking signal spends equal time at logic xe2x80x9c0xe2x80x9d and logic xe2x80x9c1xe2x80x9d).
At times, a system may require more than one clock signal. In one known system, one clocking signal is selected from two or more clocking signals. For example, if a 2:1 multiplexer is being used, first and second clocking signals are provided as inputs having different frequencies. Based on the xe2x80x9cselectxe2x80x9d input of the multiplexer, one of the clocking signals is provided at the output of the multiplexer. When the select input changes, the output changes to the other of the clocking signals.
One problem seen with this system is that the output signal typically does not provide a smooth transition between the two clocking signals. For example, the switching of the select signal from one level to another may result in an unwanted spike in the output clocking signal. Because the clocking signal is supplied to other components, such a spike could result in errors in these components.
One way to attempt to compensate for this spike is to provide a falling-edge flip-flop to supply the select input to the multiplexer. In such a system, a falling-edge flip-flop is coupled to the select input of the multiplexer described above. The loading input to such a flip-flop would be the select signal and the clocking input would be supplied, for example, by the first clocking signal. Accordingly, after the select input signal changes to select the second clocking signal, it is not supplied to the multiplexer until the first clocking signal hits a falling edge. Because the second clock may be in the middle of an asserted clock pulse, this may also lead to a glitch in the output signal (e.g., an unintended transition from 1 to 0 in the clocking signal).
In view of the above, there is a need for an improved multiplexing circuit that supplies clocking signals without errors during transitions from one clocking signal to another.